1. Field of the Invention
The present invention relates to an offset voltage calibration method and related apparatus and amplifier, and more particularly, to an offset voltage calibration method capable of precisely reducing the effect of input offset voltage and related apparatus and amplifier.
2. Description of the Prior Art
An operational amplifier is an important component of all kinds of circuits, such as analog-to-digital converters, charge pumps, filters, buffers, etc. Due to fabrication process variations or material factors, the operational amplifier may have certain non-ideal characteristics. For example, an ideal operational amplifier can provide zero output voltage with zero differential input voltage. However, output voltage of a practical operational amplifier may be non-zero for zero differential input voltage in practice. In other words, the practical operational amplifier has a direct current (DC) input offset voltage due to non-ideal factors, resulting in the output of the operational amplifier being nonzero with zero differential input voltage. Therefore, the DC input offset voltage effect will reduce the precision of the operational amplifier. If the DC input offset voltage is too great, the offset effect may seriously affect overall circuit performance.
To eliminate the input offset voltage of the operational amplifier, the prior art has presented many offset voltage calibration methods and related devices for performing an offset voltage calibration process. In general, the offset voltage calibration process can be performed during the integrated circuit (IC) manufacturing process, such as at a chip probing (CP) or final testing (FT) stage. The offset voltage calibration process can also be performed by external components for reducing the offset effect. Additionally, the offset voltage calibration process can be performed through the amplifier circuit internal to the IC according to a predetermined operation sequence, which is usually called auto-calibration.
For example, please refer to FIG. 1, which is a schematic diagram of an offset voltage calibration system 10 according to the prior art. The offset voltage calibration system 10 utilizes a digital trimming calibration method to overcome the offset voltage effect. The amount of offset error caused by the input offset voltage is often represented as a proportion of the input offset voltage to the amount of voltage variation value of a single least significant bit (LSB), which is represented in LSB. As shown in FIG. 1, when the offset voltage calibration system 10 is operated in a calibration mode, a logic unit 104 controls a counter 106 and a digital-to-analog converter 108 to progressively adjust the internal circuitry of an operational amplifier 102 to decrease the input offset voltage according to the output situation of the operational amplifier 102 until the output of the operational amplifier 102 is changed from high (low) logic level to low (high) logic level, i.e. a state change operation occurs. However, the smaller input offset voltage can not be amplified enough at the output of the operational amplifier 102 in the last stage of the calibration process due to finite open loop gain, so that the logic unit 104 can not accurately judge the state change operation of the operational amplifier 102. In such a condition, the calibrated input offset voltage which had been already adjusted to an empty zone nearby the zero offset point may be over-calibrated by another one LSB, thus the calibrated input offset voltage adjusted to the empty zone will be further calibrated to an error zone instead, resulting in an over-calibrated and inaccurate calibration process. On the other hand, when voltage value of the input offset voltage approaches zero, such as less than 1 LSB, the speed of the state change operation may be less than both clock speed of the counter 106 and the digital-to-analog converter 108, which means that the state change operation of the operational amplifier 102 becomes very slow and cannot be completed in one clock period. In other words, the counter 106 continues to count and then the over-calibrated situation occurs during the duration of the change state operation of the operational amplifier 102. As a result, the range of the empty zone and the error zone may be enlarged so as to increase the distribution of the input offset voltage. Therefore, the conventional method is not capable of achieving an accurate calibration result effectively.
Please refer to FIG. 2, which is a schematic diagram illustrating the distribution of input offset voltage according to the prior art. Through the above-mentioned calibration process of the offset voltage calibration system 10, when the input offset voltage falls within the empty zone EZ1, i.e. the voltage value of the (calibrating) input offset voltage is small enough, the logic unit 104 can not accurately judge whether the state change operation of the operational amplifier 102 is done, causing an incorrect judgment, so that the calibration process continues even if the state change operation has finished. Or, because the state change operation of the operational amplifier 102 occurs too slowly and can not be completed in one clock period, the counter 106 keeps on counting, resulting in over-calibration. In such a condition, as shown in FIG. 2, the input offset voltage calibrated into the range of the empty zone EZ1 may be over-calibrated by one extra LSB to the error zone ER1, so that the distribution of the input offset voltage can not be concentrated at zero offset point and further create an empty zone offset. In short, the effect of the input offset voltage can not be effectively minimized by the calibration process of the offset voltage calibration system 10, and this may affect performance and application range of the amplifier 102.